The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advancements to be realized, similar developments in IC processing and manufacturing are needed.
For example, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One type of the multi-gate devices is FinFETs—transistors with a fin-like semiconductor channel (“fin”) and a gate electrode engaging the fin on two or three sides thereof.
Typical methods of forming fins include a replacement fin approach and a strain relaxed buffer (SRB) approach. Both approaches have their drawbacks. A typical replacement fin approach forms dielectric trenches over a substrate and epitaxially grows semiconductor fins over the substrate and in the dielectric trenches. Defects typically exist on the interface between the semiconductor fins and the surrounding dielectric material. A typical SRB approach forms thick epitaxial films (e.g., over 1 micron (μm)) over an entire wafer, and etches the epitaxial films to form semiconductor fins. Lattice mismatch between the upper epitaxial films and the substrate are gradually decreased to provide quality epitaxial layers. However, thick epitaxial films over an entire wafer could result in severe crosshatch pattern defect, in addition to increased material costs.
Accordingly, new and improved methods for forming fins are desired.